Prof Rob Maunder introducing the Turbo code demo at MWC19 for low latency, low power URLLC. This includes the full 3GPP compliant chain in FPGA.
Turbocoding is used for error correction in LTE and now in LTE URLLC which has been introduced in 3GPP release 15.
This brings a new challenge because the time that’s available for processing the turbo encoding and in particular turbo decoding has been reduced by seven times in LTE URLLC.
This is a particular challenge for the turbo decoding, where there’s a bottleneck imposed on the degree of parallel processing that can be used and conventional implementations simply can't meet the latency requirement of LTE URLLC.
Accelercomm has addressed this challenge by developing a novel memory architecture which allows us to unlock an arbitrarily high degree of parallel processing and meet the latency requirement of LTE URLLC
We’re here at mobile world congress to demonstrate our IP. We have it here running on an arria 10 FPGA board and we have a graphical user interface which quantifies the error correction capability, the throughput and the latency of our IP.
Our IP is available for both FGPA and ASIC and it’s scalable so we can adjust the degree of parallel processing to match the particular latency and throughput requirements of your application and what's more we’ve implemented not only the turbo decoding core, but all of the other chain components that go with it, including CRC rate matching, hybrid ARQ, code block segmentation. So this makes it much easier for you to integrate.
This is important because alternative suppliers provide only the core and with an interface that is really inconvenient, it requires you to separate your inputs into partitions of an inconvenient size.
So please get in touch if we can help you with LDPC and if you’d like to receive any datasheets from us.