AccelerComm's LDPC channel code is a 3rd of the size of it's competition providing high performance low power 5G NR solutions in FPGA and ASIC. This is a fully compliant 3GPP chain including rate matching, HARQ, interleaving etc. Prof. Rob Maunder discusses LDPC code in these two short videos.
The LDPC code of 5G New Radio has a different structure to that of WiFi and every applications of LDPC before.
Some providers of IP for LDPC decoding have taken their previous implementations from wifi and DVB and they’ve tweaked them and they've adjusted them to meet the requirements, the specification for 5G new radio, but this has meant that they haven’t been able to exploit the very particular structure that the LDPC and LDGM concatenation gives.
AccelerComm has designed an LDPC decoder from scratch specifically for the particular structure of the 5G New Radio LDPC code.
We've done this at the algorithm level and the architectural level as well, this brings very significant advantages in terms of hardware efficiency. By designing specifically for the 5G New Radio LDPC code we're getting hardware efficiencies two times better than those of other solutions.
This brings us very significant advantages in terms of hardware efficiency. Our hardware efficiency is double that of other solutions that are available, thanks to our novel innovations
Our IP is available for both FPGA and ASIC and we’re implementing not just the LDPC core, but all of the chain components that go with it, including CRC rate matching hybrid ARQ.
This is really important because other suppliers are providing only the core and have a complicated interface that requires you to segment your inputs into inconveniently sized partitions.
So please get in touch if we can help you with LDPC and if you’d like to receive any data sheets from us.