3GPP Compliant LDPC Encoding/Decoding Chain

Our LDPC encoding and decoding IP for the 3GPP New Radio uplink and downlink data channel includes the entire processing chain, to provide quick and easy integration and minimise the amount of extra work needed. The LDPC core uses novel layer belief propagation schedules with early termination, in order to achieve compromise-free error correction performance with high hardware efficiency. Our decoding IP has several parameters, which can be adjusted at synthesis-time to scale the parallelism, latency and throughput.

5G Technical Data CTA

The Accelercomm LDPC IP is optimized and configurable to support high performance base-station solutions or low power (small size) mobile terminal solutions.

Features

  • Fully compliant with the 3GPP NR standard for PDSCH, PUSCH. Supports the full range of uncoded and encoded block sizes.
  • Implements the entire LDPC encoding and decoding chain in 3GPP TS38.212. 
  • High error correction performance from LDPC decoder core.
  • Tightly integrates the components in the chain to reduce area usage and latency.
  • Simple interface, quick to integrate – all parameters are internally calculated

Functional Specifications

Encoder

Decoder

CRC encoding

CRC decoding

LDPC encoding (basegraph 1

and 2, all Z-values)

LDPC decoding (basegraph 1

and 2, all Z-values)

Rate matching (incl. repetition)

HARQ combining

Bit-level interleaver

Filler bits insertion/removal

Filler bits insertion/removal

Inverse Rate matching (incl. repetition)

 

Bit-level de-interleaver

 

Soft-output interface (optional)

 

Re-encoded output stream (optional)

Core Benefits

  • FPGA support for Xilinx, Intel and Achronix
  • Optimised for ASIC process
  • Optimised software solution on Intel Architecture and AVX512 acceleration
  • Matlab & C Models available
  • Configurable parameters for power & performance optimisation
  • Scalable design
  • Standard AXI interfaces

What is Supported in the 3GPP NR LDPC Code

The AccelerComm LDPC encoder and decoder chain is compliant with the LDPC code blocks for both uplink and downlink, including the CRC, LDPC core, bit selection and bit interleaving procedures defined in TS 38.212. More specifically, the AccelerComm LDPC decoder supports the following parts of TS 38.212:

  • the CRC16 and CRC24A transport block CRC parts of Section 5.1 of TS 38.212;
  • the CRC24B code block CRC and filler bit insertion parts of Section 5.2.2 of TS 38.212; 

  • all of Section 5.3.2 of TS 38.212, namely LDPC coding and the puncturing of the first 2Zc systematic bits; 

  • the bit selection part of Section 5.4.2.1 of TS 38.212 including HARQ combining, but not the deter- mination of Nref and Er; 


all of Section 5.4.2.2 of TS 38.212, namely bit interleaving.

 

Simplified block diagram of the LDPC decoder chain

The numbers in parenthesis refer to relevant 3GPP specification section.  

Simplified block diagram of the LDPC encoder chain

The numbers in parenthesis refer to relevant 3GPP specification section.

SD-FEC integration with AccelerComm components

At AccelerComm we have created an encode and decode wrapper for the Xilinx SD-FEC to enable full 3GPP compliance.