3GPP Compliant LDPC Encoding/Decoding Chain

Our LDPC encoding and decoding IP for the 3GPP New Radio uplink and downlink data channel includes the entire processing chain, to provide quick and easy integration and minimise the amount of extra work needed. The LDPC core uses novel layer belief propagation schedules with early termination, in order to achieve compromise-free error correction performance with high hardware efficiency. Our decoding IP has several parameters, which can be adjusted at synthesis-time to scale the parallelism, latency and throughput.

The Accelercomm LDPC IP is optimized and configurable to support high performance base-station solutions or low power (small size) mobile terminal solutions.

Features

  • Fully compliant with the 3GPP NR standard for PDSCH, PUSCH. Supports the full range of uncoded and encoded block sizes.
  • Implements the entire LDPC encoding and decoding chain in 3GPP TS38.212. 
  • High error correction performance from LDPC decoder core.
  • Tightly integrates the components in the chain to reduce area usage and latency.
  • Simple interface, quick to integrate – all parameters are internally calculated

Functional Specifications

Encoder

Decoder

CRC encoding

CRC decoding

LDPC encoding (basegraph 1

and 2, all Z-values)

LDPC decoding (basegraph 1

and 2, all Z-values)

Rate matching (incl. repetition)

HARQ combining

Bit-level interleaver

Filler bits insertion/removal

Filler bits insertion/removal

Inverse Rate matching (incl. repetition)

 

Bit-level de-interleaver

 

Soft-output interface (optional)

 

Re-encoded output stream (optional)

Core Benefits

  • FPGA support for Xilinx, Intel and Achronix
  • Optimised for ASIC process
  • Matlab & C Models available
  • Configurable parameters for power & performance optimisation
  • Scalable design
  • Standard AXI interfaces

Lead Partner Programme

If you are interested in hearing more, please complete the form and we will contact you to discuss how you can receive early deliverables and influence the key design features for our 3GPP compliant LDPC chain for 5G NR. 

Our goals are always finding the optimal trade-off between the following seven implementation characteristics:

  • Error correction/detection capability
  • Throughput
  • Latency
  • Memory/logic hardware resource requirements
  • Power consumption
  • Features (e.g. soft-in soft-out)
  • Ease of integration

 

Best Regards

The Accelercomm Team